An Area Efficient Hierarchical Carry Save Algorithm (HCSA) using VHDL

Journal

International Journal of Digital Applications and Contemporary Research (IJDACR)

ISSN

2319-4863

Volume / Issue

Vol.10 · Issue 6

Published

January 2022

Access

Open Access

Licence

CC BY-NC-SA 4.0

Krishan Kumar Safi Ankit Pandit Ashish Chouhan

The carry-save adder diverts the carry towards LSB of partial product and in order to decrease the final bits of the adder, CSA generates LSBs. This helps in implementing the pipeline approach which in turn improves the performance. In this proposed scheme the main motive is to remove the independent accumulate stage which creates a huge delay and merge it with the partial product’s compression stage. This paper proposed a Hybrid carry-save algorithm for a 32-bit adder with optimized area and speed. The proposed system is developed in VHDL and synthesized in Xilinx.

CSA LSB VHDL XILINX etc.

Krishan Kumar Safi, Ankit Pandit, Ashish Chouhan (2022). An Area Efficient Hierarchical Carry Save Algorithm (HCSA) using VHDL. International Journal of Digital Applications and Contemporary Research (IJDACR), Vol.10, Issue 6. ISSN: 2319-4863.

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