Volume 14 Issue 3  ·  ISSN: 2319-4863  ·  Monthly Publication editor@ijdacr.com
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Research Article

Area Efficient Design of Five Stage Pipelined RISC Processor

Shahnawaz Khan  ·  Prabhat Pandey

IJDACR Vol.7 No.2 (September 2018) ISSN 2319-4863 Open Access Peer Reviewed

Journal

International Journal of Digital Applications and Contemporary Research (IJDACR)

ISSN

2319-4863

Volume / Issue

Vol.7 · Issue 2

Published

September 2018

Access

Open Access

Licence

CC BY-NC-SA 4.0

Authors

Shahnawaz Khan Prabhat Pandey

Abstract

This paper proposes the design of a 32 bit RISC (Reduced Instruction Set Computer) processor. The design helps to improve the speed of the processor and to give the higher performance of the processor. It has 5 stages of pipeline viz. instruction fetch, instruction decode, instruction execute, memory access and write back all in one clock cycle. The control unit controls the operations performed in these stages. All the modules in the design are coded in VHDL.

How to Cite

Shahnawaz Khan, Prabhat Pandey (2018). Area Efficient Design of Five Stage Pipelined RISC Processor. International Journal of Digital Applications and Contemporary Research (IJDACR), Vol.7, Issue 2. ISSN: 2319-4863.

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Article Info

Journal IJDACR
Volume Vol. 7
Issue No. 2
Month September
Year 2018
ISSN 2319-4863
Access Open Access

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