REVIEW :- LOW POWER DOUBLE TAIL COMPARATOR BY CLOCK GATING

Journal

International Journal of Digital Applications and Contemporary Research (IJDACR)

ISSN

2319-4863

Volume / Issue

Vol.5 · Issue 1

Published

August 2016

Access

Open Access

Licence

CC BY-NC-SA 4.0

Balmit Singh Dinesh Chand Gupta

The need for ultra low-power, area efficient, and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to maximize speed and power efficiency. In the previous paper[19], an analysis on the delay of the dynamic comparators will be presented and analytical expressions are derived. From the analytical expressions, designers can obtain an intuition about the main contributors to the comparator delay and fully explore the tradeoffs in dynamic comparator design. Based on the presented analysis, a new dynamic comparator is proposed, where the circuit of a conventional double tail comparator is modified for low-power and fast operation even in small supply voltages.

Balmit Singh, Dinesh Chand Gupta (2016). REVIEW :- LOW POWER DOUBLE TAIL COMPARATOR BY CLOCK GATING. International Journal of Digital Applications and Contemporary Research (IJDACR), Vol.5, Issue 1. ISSN: 2319-4863.

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