Research Article
Sneha Devasthali · Preet Jain
Journal
International Journal of Digital Applications and Contemporary Research (IJDACR)
ISSN
2319-4863
Volume / Issue
Vol.5 · Issue 8
Published
March 2017
Access
Open Access
Licence
CC BY-NC-SA 4.0
Most of the FPGA features communicate with each other through bus means. Each block is designed for a specific bus. The buses related to this work is the AMBA bus and the Wishbone bus. It works with the master / slave architecture. The AMBA bus is extensively utilized in the system on chip solution for interaction with different peripheral. The proposed work includes the regular AMBA specifications of (1) burst transfer, (2) Several bus masters, (3) single clock edge transition and (4) Split transaction. The data transfer is accomplished by a single bus master at a while. Despite the fact that the arbitration protocol is settled, any arbitration algorithm, for example, fair access or highest priority can be actualized relying upon the application necessities. VHDL code is utilized to develop the design and it is synthesized on Virtex-2 series.
Sneha Devasthali, Preet Jain (2017). Multi-Master Supported Arbiter in AHB System. International Journal of Digital Applications and Contemporary Research (IJDACR), Vol.5, Issue 8. ISSN: 2319-4863.
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