A SURVEY ON HIGH PERFORMANCE BINARY TO BCD CONVERSION FOR DECIMAL ADDER

Journal

International Journal of Digital Applications and Contemporary Research (IJDACR)

ISSN

2319-4863

Volume / Issue

Vol.4 · Issue 9

Published

April 2016

Access

Open Access

Licence

CC BY-NC-SA 4.0

Devendra Kumar Verma Vikas Kumar Mishra

In view of increasing eminence of commercial, economic and Internet-based applications that process data in decimal arrangement, Synthesis results for 2, 4, 8, and 12 operands and 8 decimal digits provide useful statistic in determining each adder’s performance and scalability. There is a renewed interest in providing hardware support to handle decimal data. In this paper, a new architecture decimal addition of binary coded decimal (BCD) operands, which is the main design part of high speed low power multi operand binary adder are compared. Based on this add-3 digit BCD adder new architectures for higher order (n-digit) BCD adders such as ripple carry adder are developed.

Devendra Kumar Verma, Vikas Kumar Mishra (2016). A SURVEY ON HIGH PERFORMANCE BINARY TO BCD CONVERSION FOR DECIMAL ADDER. International Journal of Digital Applications and Contemporary Research (IJDACR), Vol.4, Issue 9. ISSN: 2319-4863.

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